The present invention relates to semiconductor devices and to layout methods, and more particularly to a current mirror semiconductor device and a layout method of the same, which can reduce mismatching layout errors of a semiconductor device having a mirror structure.
Typically, semiconductor devices are formed with transistors made by a combination of different masks. These masks are manufactured to produce several tens of layers and are combined, and patterns of the masks are formed using a photo device. Dies within a wafer are designed under the same or similar conditions, but slight differences in positions within the wafer may occur due to various variables during processing. These differences often occur due to mismatching of the various combinations of masks, etc. A mismatch in the combination of the masks leads to mismatch errors in transistors that often times result in performance degradation of the transistors.
Of particular interest is semiconductor devices that are configured to have current mirror structures, for example, groupings of transistors configured as voltage generators and/or as sense amplifiers, or the like. These types of semiconductor devices seem to be more prone to being adversely affected by mismatching a combination of the masks.
A mismatch of transistors occurring during the combination of masks in a semiconductor device having a mirror structure will be described with reference to FIGS. 1 to 3.
As depicted in FIG. 1, a typical voltage generator includes PMOS transistors P0, P0B; NMOS transistors N0, N0B, both of which have a mirror structure; an NMOS transistor N1 holding bias voltage; and a PMOS transistor P1 selectively pumping output voltage.
Respective gates of the NMOS transistors N0, N0B receive a reference voltage VREFC and a comparison voltage (for example, a core voltage VCORE) and a gate of the NMOS transistor N1 receives a voltage generating enable signal EN.
The voltage generator compares the core voltage VCORE to the reference voltage, thereby selectively driving the PMOS transistor P1 and outputting the core voltage VCORE with the same voltage level as that of the reference voltage VREFC. A layout of the voltage generator corresponding to an the region including the mirror structure of FIG. 1 will be described with reference to FIG. 2.
The PMOS transistors P0, P0B arranged within an N well region 10 and the NMOS transistors N0, N0B arranged within a P-type substrate 20 have a symmetric structure to each other based on a Y-axis, i.e., a commonly shared lengthwise boundary.
Specifically, the PMOS transistor P0 is arranged in order of a source S0 to a drain D0 along one direction (in FIG. 2, proceeding from a left to right direction). On the other hand, the complementary PMOS transistor P0B is arranged in order of a drain D0B to a source S0B with respect to proceeding from the left to a right direction.
Likewise, the NMOS transistor N0 is arranged in order of a source S1 to a drain D1 with respect to proceeding from the left to right direction and the NMOS transistor N0B is arranged in order of a drain D1B to a source S1B with respect to proceeding from the left to right direction.
A drain D1 of the NMOS transistor N1 is arranged at a node ND1 to which the sources of the NMOS transistors N0, N0B are commonly connected.
If the PMOS transistors P0, P0B and the NMOS transistors N0, N0B are designed under the same conditions and are formed at defined positions irrespective of alignment variables during a masking process, the resultant voltage generator prevents the mismatch to exert the same performance and reduce the offset, making it possible to assure mass productivity and to increase reliability of the semiconductor device.
Furthermore, if the NMOS transistor N1 is connected to a point which is an exact half from the sources S1, S1B of the NMOS transistors N0, N0B, then the mismatch alignment errors of the NMOS transistors N0, N0B can be reduced.
However, when the transistors are configured in a current mirror type structure as shown in FIG. 2, then these transistors are often symmetrically laid out with respect to one direction (herein, along a Y-axis direction also referred to a commonly shared lengthwise boundary). As a result of this symmetrically laid out design, the resultant transistors suffer a large number of mismatch errors as a result of the mismatch alignment of the plurality of transistors employing these combinations of masks.
As depicted in FIG. 3a, when a contact mask is misaligned by being inclined to one direction, for example, a left direction from a reference position, a contact distance CD1 of the gate G1 and the drain of the NMOS transistor N0 is shorter than a contact distance CS1 of the gate G1 and the source thereof. On the other hand, a contact distance CD1B of the gate G1B and the drain of the NMOS transistor N0B is longer than a contact distance CS1B of the gate G1B and the source thereof.
As depicted in FIG. 3b, when a gate mask is misaligned by being inclined to another direction, for example, a right direction from the reference position, the gate G1 of the NMOS transistor N0 is overlapped with a portion of the drain D1 thereof, while the gate G1B of the NMOS transistor N0B is overlapped with a portion of the source S1B thereof.
As depicted in FIG. 3c, when a mask for a device isolation layer is misaligned by being inclined toward one direction, for example, a right direction from the reference position, the source S1 of the NMOS transistor N0 is reduced and the drain D1 thereof is increased, while the source S1B of the NMOS transistor N0B is increased and the drain D1B thereof is reduced.
Generally, drain-source current Ids of the transistor is proportional to {(Vgs−Vt)*Vds−the square of ½ Vds} in a linear region and is proportional to {the square of (Vgs−Vt)} in a saturation region. As a result of this relationship, the drain-source current Ids exhibits a proportional relation with the source of the transistor in the linear region and the saturation region.
However, as shown in FIGS. 3a to 3c, when the transistors are not accurately formed at the positions defined in the design of the transistors due to mismatch errors in the combination of the masks, the threshold voltage Vt of the transistor and drain-source current Idsat value in the saturation region are changed.
Therefore, the performance of semiconductor devices, in particular current mirror configurations, can be adversely affected by mismatch errors when combining the masks to build symmetrically laid out devices.
Also, even though the NMOS transistor N1 is connected at a point which is substantially at an exact halfway point from the sources of the NMOS transistors N0, N0B; these mismatch errors can still adversely affect the resultant NMOS transistor N0 having the same arrangement structure and the NMOS transistor N0B having the opposite arrangement structure.